SNN / DVS Projects
A framework for designing and evaluating spiking neural networks with hardware constraints in mind, targeting efficient deployment on neuromorphic and edge platforms.
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This framework provides a structured approach to building spiking neural networks that are designed from the ground up with target hardware in mind. Rather than training a network and then attempting to port it, hardware constraints — such as on-chip memory, fan-in limits, and supported neuron models — are incorporated throughout the design and evaluation loop.
Neuromorphic chips such as Intel Loihi, BrainScaleS, and SpiNNaker each expose different constraints. Networks designed without awareness of these constraints often fail silently or degrade significantly upon deployment. This framework makes those constraints explicit during training and architecture search.
The framework includes hardware-parameterised neuron models, constraint-aware pruning, and a benchmarking suite that evaluates accuracy, spike rate, memory footprint, and estimated energy consumption across multiple target platforms.
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